1. Field of the Invention
The present invention relates in general to data processing systems and in particular to data processing systems which dynamically allocate main memory for use by the operating system software and application software. Still more particularly, the present invention relates to systems which can directly manipulate pages of memory by modifying the translation table associated with the dynamically allocated main memory.
2. Discussion of the Prior Art
In computer systems it is customary that there be one-to-one correspondence between the memory address produced by the processor and a specific area in the physical memory of the system. It is an error for the processor to request access to an address which does not have an associated physical memory area. This limits the operating system and applications to an address space determined by the actual physical memory installed in the system. Modern computer systems have overcome this limitation through the use of virtual memory which implements a translation table (TT) to map program addresses to real memory addresses.
With virtual memory the program works in an address space limited only by the processor architecture. It is a function of the operating system to ensure that the data and code a program is currently using is in main memory and that the translation table can map the virtual address to the real address correctly. In a virtual memory system the allocation of memory is most commonly performed by the operating system software. This requires an interrupt of the instruction sequence so that the privileged kernel code can allocate physical memory to the area being accessed so that normal program flow can continue without error. This interrupt and the kernel processing to allocate physical memory requires a significant amount of processing time and upsets the normal pipelining of instructions through the CPU.
There currently exist schemes for reducing operating system process interruptions. For instance, the reference entitled “Design and Analysis of Internal Organizations for Compressed Random Access Memories” by Peter A. Franaszek and John T. Robinson, IBM Research Report RC21146(94535), dated Oct. 28, 1998, describes a low level main memory design for storing compressed data that includes a directory portion and a collection of fixed size blocks which are used to store lines in compressed format. In the memory storage scheme described herein, highly compressible lines may be stored entirely within a directory entry; otherwise, the directory entry points to one or more of the fixed size blocks which are used to store the line in compressed format. The system further makes use of page tables which translate virtual addresses to real addresses which correspond to the location in the directory of the directory entry for the line and which includes information pertaining to blocks holding a compressed line. Specifically, the information in a directory entry includes flags, fragment combining information, and, assuming fixed size entry structure pointers to one or more fixed size blocks. On a cache miss, the memory controller and decompression hardware finds the blocks allocated to store the compressed line and dynamically decompresses the line to handle the miss. Similarly, when a new or modified line is stored, the blocks currently allocated to the line are made free (if the line currently resides in the RAM), the line is compressed, and then stored in the RAM by allocating the required number of blocks.
Furthermore, U.S. Pat. No. 5,761,536 is directed to a memory organization technique utilizing a compression control device for storing variable length objects (compressed memory) in fixed-size storage blocks by enabling fixed size storage blocks to receive remaining portions (leftover compressed memory pieces or fragments) of variable length objects that take up less than a full fixed-size storage block. The system thus reduces memory fragmentation.
U.S. Pat. No. 5,864,859 is directed to a compression store addressing technique for storing variable length objects (compressed lines, each representing, e.g., ¼ of a page) in fixed size blocks so that accessing an individual line may be accomplished quickly and with little change to existing software. In particular, the beginning of any line within a page may be accessed with a single pointer plus an offset. Associated with the compression store is a list of free or available blocks (free list) which is accessed for enabling variable length object storage.
Aforementioned commonly-owned, co-pending U.S. patent application Ser. No. 09/627,516 addresses the desirability to provide a mechanism that enables the physical memory to be dynamically allocated in a manner such that the interruption in program flow is eliminated, and, furthermore, provides a mechanism for facilitating the management of memory pools so that the various processes and users may share the system resources fairly.
It is the case that certain simple operations in computer systems such as clear block and move block are commonly performed on large blocks a contiguous memory bytes called pages. These operations often require that the processor access each individual byte in the page or pages. This makes the operations take an appreciable amount of time and cause the total contents of the page or pages to be loaded into each level of the memory cache hierarchy. This cache damage causes further performance impacts since it evicts other data and programs which are being used by the processor. Subsequent accesses of this purged data will take additional time to reload the appropriate data into the caches
It would thus be highly desirable to provide in a computer system using dynamically allocated physical memory and a translation table for managing this memory, a mechanism for performing these page operations without requiring the use of the processor.